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This article discussed the latest developments of RISC-V computing for storage applications based upon presentations at the 2020 RISC-V Summit as well as Marvell Technologies advances in storage controllers, NICs and preamps to support customized SSDs, Ethernet Bunch of Flash and advanced nearline HDDs.

Reduced Instruction Set Computing (RISC) is a computer architecture that has instructions that can be executed in one computer clock cycle.  Multiple instructions are often needed to complete a given task.  Complex Instruction Set Computing (CISC) completes a task in as few lines of software code as possible, thus using complex instructions that may take multiple computer clock cycles to complete.  RISC offers advantages in terms of less complex computing hardware and enabling pipelining (out-of-order command execution).  RISC was originally introduced in the 1970’s, but it took a long time to get commercial acceptance due to a lack of software support.  The Intel X86 is one of the few chips which retain the CISC architecture.

RISC-V is an open and free RISC instruction set architecture.  The RISC-V community is promoting the use of RISC-V processors, hardware and software.  At the recent RISC-V Summit there were talks by Western Digital and Seagate on their use of RISC-V processors in their storage devices and systems.

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