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Oxford, UK – January 25th, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the latest addition to the Imperas RISC-V Verification IP (VIP) solutions with the Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). These tests extend the current Imperas range of tests for ratified and near-ratified specifications tests, and complement the de facto industry adoption of the Imperas RISC-V verification reference model.

Processor verification is the essential focus of any development team. Design bugs that are caught early help projects complete on schedule and provide timely solutions to the target market. The impact of late-stage bugs, and associated costs, can be significant. One often-quoted example is the Intel Floating Point bug discovered in deployed devices by end-users in 1994. The total economic impact of this issue was reported at the time as a pre-tax charge of $475m.


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