RISC-V is, like x86 and ARM, an instruction set architecture (ISA). Unlike x86 and ARM, it is a free and open standard that anyone can use without getting locked into someone else’s processor designs or paying costly license fees.
RISC-V (pronounced RISC-5) is the brainchild of UC Berkeley professors David Patterson and Krste Asanović. Patterson has a talent for catchy acronyms and architectures as a developer of RISC (Reduced Instruction Set Computing) and RAID (Redundant Array of Inexpensive Disks) in the 1980s. They outlined the case for RISC-V in this paper.
An ISA as an interface — similar to an Application Programming Interface (API) — for CPU operations. A compiler or interpreter translates your high-level language, such as C, into ISA commands for the processor to perform work.
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