RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the organization teamed with OneSpin and several other verification partners to develop the CORE-V-VERIF silicon-proven, industrial-grade functional verification platform. This platform was used to execute the complete verification of the CORE-V CV32E40P and is currently being used to verify the CV32A6 and CV64A6 cores.
The CV32E40P core will be used for high-volume, commercial chip projects with strict integrity criteria. The OpenHW Group recognized that the use of simulation alone would leave the core vulnerable to undetected critical bugs, incomplete coverage, and/or unnoticed hidden instructions—and they fully recognized that any of these verification shortcomings could result in functional errors, safety issues, and security holes. To remedy this, the CORE-V-VERIF platform goes beyond simulation to include OneSpin’s unique formal verification technology, which has proven vital to achieving speedy, successful, and bug-free delivery of the CV32E40P core.