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Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning | British Computer Society Open Source

By RISC-V Community NewsFebruary 24, 2021February 25th, 2021No Comments

Presented by Pete Alexander, John Holden, Harry Cooper, Byron Theobald, Aaryaman Bhattacharya, Matthew Johns, University of Southampton

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Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning | British Computer Society Open Source

Previous PostRISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension | Design & Resuse

Next PostOpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP

Stay Connected With RISC-V