Next week, I will be moderating a panel at the virtual DVCon on the subject of open-source verification. I thought it would be good to advertise the event on LinkedIn to see if anyone wanted to send me well-structured questions for the panelists. What happened surprised me a little because the discussions almost exclusively went to the need for open-source verification tools. In my opinion, they are totally missing the biggest opportunity.
The RISC-V ISA, and the many implementations of it, have re-ignited the open-source discussion within the semiconductor space. But RISC-V is a piece of IP, and to implement that in silicon requires a long list of tools to bring it to realization. The value of those tools is somewhere in the vicinity of $10B. While it is true that many of those tools are available as open source, they rarely are used outside of academia. It is very clear why — the cost of a chip failure is so high that spending just a few percent of the cost of development on tools reduces risk enough to justify that cost.