Using gem5 and RISC-V simulation to enable the optimization of heterogeneous architectures | HiPEAC

This tutorial will provide an introduction to architectural simulation using the gem5-X simulation framework (which is an extended and improved version of the gem5 simulator) and demonstrate how the gXR5 extensions for gem5-X can be used to simulate a full-system Linux-capable RISC-V architecture. Furthermore, we will showcase the benefits of full-system gem5 simulation for architectural exploration and optimization by showing how we can simulate three different architectural enhancements using gem5: (1) in-cache computing, (2) analog in-memory compute cores and (3) wireless interconnects; and we will describe how architectural evaluation (in terms of performance and power) can be performed. This one-day tutorial will start by providing an overview on the capabilities of gem5-X and gXR5, followed by detailed descriptions of the three architectural enhancements proposed and the methodology followed. The afternoon session will include a hands-on technical session where we will get the audience acquainted with gem5-X and gXR5, showing them how to use these extensions to perform their simulations.