Munich, Germany – March 9th, 2021 – Codasip, the leading supplier of customizable RISC‑V processor IP, announced three commercially licensed add-ons to the Western Digital SweRV Core® EH1. The add-ons enable the SweRV Core EH1 to be designed into a wider range of applications.
The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. Codasip is now offering three add-on options to EH1:
- A floating-point unit (FPU) that supports the RISC-V single precision [F] and double precision [D] instructions.
- A data cache with configurable size, associativity, and cache lines. It can be configured with either AXI or AHB-Lite interfaces.
- Additional instructions for bit manipulation which can be beneficial for error detection/correction, DSP, and security algorithms.