Presented by Ibrahim Abu Kharmeh, Huawei Bristol, UK RISC-V is an open source fast growing ISA designed at the University of California, Berkeley. The ISA was designed to target various wide range of applications starting from HPC to Embedded Systems. For RISC-V to be competitive in embedded space, its code size density has to be at least on par or better than commercial alternatives. While RISC-V contains several features like variable instruction length and compressed instruction that should help achieving that. Several benchmarks [1] indicate that RISC-V code density is worse than that of these alternatives. Luckily, RISC-V was designed to accommodate for extensions to enhance various aspects of its performance. One of those extensions is Zce, this extension purpose is to help close the gap of code density with these alternatives. In this presentation, I will present the evaluation criteria used for comparison, review the main contributing factors to the worse code density performance, review the main Zce instructions for better code density (PushPop, TBLJAL and Multimove), and present their approximate savings. References [1] Perotti, Matteo, et al. “HW/SW approaches for RISC-V code size reduction.” Workshop on Computer Architecture Research with RISC-V (CARRV 2020)