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SEGGER and Codasip Announce Cooperation on RISC-V

By June 21, 2021June 30th, 2021No Comments

SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box.

SEGGER’s J-Link debug probe supports RISC-V debug on Codasip’s processor cores. Furthermore, J-Link, using the Open Flashloader concept, allows programming of flash memories connected to devices using Codasip RISC-V cores, while Embedded Studio’s Linker and Runtime Libraries are perfect for minimizing code size.

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