A quartet of computer science boffins have showcased work on bringing the OpenCL programming framework to a wide range of RISC-V chips – improving their suitability for highly parallel workloads in science and beyond.

Born at the University of California at Berkeley in 2010, following an earlier research project from the 1980s dubbed Berkeley RISC, which would eventually become the SPARC architecture, RISC-V is both free and open source. As a result, anyone can build chips implementing the RISC-V architecture and can modify and expand it at will, adding new features or tweaking existing ones as required.

A paper presented at the Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), though, concentrates wholly on off-the-shelf RISC-V chips – introducing support for the Open Computing Language (OpenCL) heterogeneous programming framework commonly used to spread scientific workloads across CPUs, GPUs, and other accelerators.

See the full article in The Register.

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