RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.
This development in the semiconductor market has been an area of much interest in different international forums. Although there are no lack of resources and events on the topic, Veriest is organizing for the first time a dedicated event for the Serbian engineering and academic community.
In this online webinar, called “5 Talks on RISC-V”, we will host top experts – from the US, Germany and Serbia – will be sharing their views – in Serbian – on different aspects of this new CPU paradigm, from ecosystem, to architecture, including design, verification and software.