While Arm cores have proven themselves reliable and are now in most mobile devices and Internet of Things (IoT) endpoints, it’s always both useful and reassuring to have an alternative, as one size does not always fit all.
Enter the RISC-V 32-bit CPU. RISC-V (pronounced risk-five) is an open-source, no royalty architecture that is the first serious competition to the entrenched Arm CPU core ecosystem in a very long time. The base RV32 variant has 31 general-purpose, 32-bit registers named x1 to x31 (register x0 is hard-wired to 0). It supports extensions to the architecture that allow flexibility for different applications. For example, when building a microcontroller, the “B” RISC-V extension supports native bit manipulation, which in my long experience with microcontrollers is an indication that the architecture is serious about the deep embedded stuff.
The challenge, however, is getting engineers to accept a new architecture. It’s always a rocky road to adoption when you go against the existing sourcing momentum.