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High-Level Synthesis For RISC-V | Brian Bailey, Semiconductor Engineering

By November 4, 2021November 8th, 2021No Comments

Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL).

There are two types of high-level synthesis (HLS) that need to be considered. The first is generic HLS, which takes a description in C, C++, or SystemC and turns it into RTL. These tools enable you to explore the design space to create an optimal architecture, and this has worked exceedingly well for algorithms that are dataflow-oriented. In fact, the tools have become better at handling control-oriented constructs over time. But can they be used to implement processors? And is there a better way?

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