RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. This modular ISA has a base instruction set and optional extension sets. Because RISC-V is free and open-source, it has gained popularity worldwide. Over 65 RISC-V cores, both commercial and open-source, are available today.
Efinix has created 3 RISC-V SoCs based on the VexRiscv core created by Charles Papon. The VexRiscv core, which won first place in the RISC-V SoftCPU contest in 2018, is a 32-bit CPU using the ISA RISCV32I with M and C extensions, has five pipeline stages (fetch, decode, execute, memory, and writeback), and a configurable feature set. Each SoC has a RISC-V processor, memory, a range of I/O, and interfaces for embedding user functions. You can easily create entire systems that include embedded compute and user-defined accelerators all in the same Titanium or Trion® FPGA.