Join Us at RISC-V Summit Europe in Munich, Germany | June 24-28

In the News

SiFive announced new, high performance RISCV cores as AMD is looking for RISCV architect? | René Rebe, Bits inside by René Rebe

By RISC-V Community NewsJanuary 6, 2022January 8th, 2022No Comments

#SiFive p650 high performance #RISCV cores w/ Vector and Hypervisor extension while AMD is hiring RISCV engineers, too?!

Watch the full video.

Previous PostCFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs | Shvetank Prakash∗, Tim Callahan† Joseph Bushagour§, Colby Banbury∗, Alan V. Green†, Pete Warden†, Tim Ansell†, Vijay Janapa Reddi∗, †Google §Purdue University ∗Harvard University
Next PostWhen You Reach The Summit, Keep Climbing | Andy Frame, SiFive

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.