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Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions | Philippos Papaphilippou, Kelly Paul H. J., and Wayne Luk

By January 6, 2022January 8th, 2022No Comments

Abstract: Simodense is a high-performance open-source RISC-V (RV32IM) softcore, optimised for exploring custom SIMD instructions. In order to maximise SIMD instruction performance, the design’s memory system is optimised for streaming bandwidth, such as very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications with custom instructions. This paper also provides insights on the effectiveness of adding FPGA resources in general purpose processors in the form of reconfigurable SIMD instructions.

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