Skip to main content

New open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification.

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the official 1.0 release of the new RVVI (RISC-V Verification Interface) as a foundation for the new RISC-V verification ecosystem. The open standard ISA (Instruction Set Architecture) of RISC-V has stimulated the interest in optimized processors across almost all market segment and application areas. Since previously SoC developers were constrained to consider only a few limited mainstream IP cores, the design freedom of RISC-V has generated significant interest for innovation. This design freedom is also migrating the verification responsibility from a few IP providers to all adopters that choose to exploit these new design freedoms of RISC-V.

Read the full announcement. 

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.