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CV32E40P Core From OpenHW Group Sets the RISC-V Quality Standard For Open-Source Hardware IP | Imperas Software Ltd.

By June 21, 2022June 27th, 2022No Comments

Imperas Software Ltd., the leader in RISC-V simulation solutions, congratulates the OpenHW Group on the announcement of the CORE-V MCU Dev/Kit project based on the high-quality CV32E40P open-source processor IP core, the first core to be fully verified within the OpenHW CORE-V family. This marks the first of many projects based on the CV32E40P, which was verified using the Imperas RISC-V golden reference model, now in development both within open-source community projects and commercial designs. Imperas is a founding member of the OpenHW Group which was established with a clear objective to drive the adoption of open-source hardware by delivering quality IP cores based on industrial strength verification and compatibility with the established commercial EDA design tools and flows. The use of the Imperas lock-step-compare methodology for the verification of the CV32E40P now sets the standard for quality verification for RISC-V processor cores, not just open-source IP.

As an open standard ISA (Instruction Set Architecture) RISC-V is a natural option for open-source hardware projects. The RISC-V specifications are based on a modular framework with many standard extensions, each with significant options and configuration flexibility. All the design flexibility of RISC-V increases the requirements for extensive verification plans, including full dynamic operations with asynchronous events and debug modes of operation. The OpenHW Verification Task Group set up the CORE-V-VERIF verification testbench to verify not just the core, but with built-in flexibility to accommodate future adopters as they extend the base core features and thus the associated test requirements.

Read the full announcement. 

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