Pavilion Panel: Those Darn Bugs | Axiomise

While the size of a computer shrank from a mainframe to a watch, an unquestionably remarkable feat, the time to verify these complex designs hasn’t. Neither have bug escapes, even though the ratio of verification engineer to designer is 5:1 for most processor design projects, and the cost of verification is 70% of a design verification budget. Even so, the 2020 Wilson Research Group report from Siemens EDA’s Harry Foster points out that 68% of ASICS go through a respin and 83% of FPGAs do not work the first time. The elusive zero bug escape is a long-held goal for silicon design houses. The question many DAC attendees ask is whether bug eradication will ever become a reality. This panel explored this topic in detail to find out what’s causing the industry to not scale verification to the point that we can sign off our chips on time, the first time with zero bugs. Moderator: Brian Bailey – Semiconductor Engineering Panelists: Ashish Darbari – Axiomise Mark Glasser- Cerebras Ty Garibay – Mythic Larry Lapides – Imperas