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‘First’ RISC-V CPU certified compliant with ISO 26262 | Steve Bush, Electronics Weekly

By October 17, 2022November 6th, 2022No Comments

Andes Technology has introduced safety-enhanced RISC-V CPU intellectual property, claiming it to be “the first to certified to be fully compliant with ISO 26262 functional safety standards for the development of automotive applications”.

SGS-TÜV Saar audited the core, called N25F-SE, and certified it to ASIL B according to ISO 26262 including Parts 2, 4, 5, 8 and 9, said Andes.

It is a 32bit RISC-V core that supports standard IMACFD extensions, integer, single precision floating point and double precision floating point instructions, as well as Andes V5 extensions, intended to boost performance and reduce code size.

Balancing operating frequency and gate count, a five-stage pipeline has been implemented, and “N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions”, said Andes.

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