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RISC-V: Dividing efficiently across different hardware

Author: Paul Curtis

In previous blog posts I have described the division algorithms SEGGER implemented in emRun. However, which algorithm is best (in terms of code size, execution speed, or power efficiency) is very dependent on the target instruction set architecture (ISA) and the way the ISA is implemented in silicon. This article explains how we help to select the best division algorithm for use.

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