Agile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips.
The initial subsystem includes all the analog IP required for a typical battery powered IoT system. These include the power management unit (PMU), a sleep management unit (SMU), and data converters detailed by eeNews Europe in April. The process agnostic, customisable and digitally wrapped analog IP subsystem will pair with a RISC-V core to form a complete design for digital chip developers.