Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced its participation at DAC 60 with panels and presentations, and exhibits and live demos at its booth 2336. A key highlight during the show is the RISC-V panel session hosted by Imperas.
Panel Session: Delivering on RISC-V’s Promise to Give Designers Freedom to Innovate – What’s Needed?
The RISC-V instruction set architecture (ISA) open standard has accelerating momentum in the semiconductor community. This is due to the open nature of the ISA, enabling users to build domain-specific processors that can help to differentiate products. Is this momentum built on real SoCs going to production? What is needed to develop a RISC-V based SoC? How mature is the specification? Is RISC-V ready for prime time? Who takes responsibility for verification?