VyperCore shows RTL simulation of RISC-V core, plans hardware

By RISC-V Community NewsJanuary 24, 2024No Comments

VyperCore in the UK has passed a major development milestone in the development of a new chip architecture starting with RISC-V.

Bristol-based VyperCore is developing an architecture to embed functions such as garbage collection to improve the performance of processors and make them more power efficient. It has shown the RTL design for the technology in a RISC-V processor running in simulation for the first time running code and plans a hardware version for June 2024.

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VyperCore shows RTL simulation of RISC-V core, plans hardware

Previous PostStarFive RISC-V SoC's Camera Subsystem Driver Added To Linux 6.8

Next PostDebugging complex RISC-V processors

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