This session will focus on a demonstration using the RISC-V specification incorporated into a Sinfonia project. Sinfonia utilizes it’s ingested knowledge of RISC-V and the enriched understanding from the LLM to support user-directed enhancements to an existing RISC-V implementation. This approach exemplifies the potential of AI to accelerate logic design and verification, offering a glimpse into future engineering capabilities available to semiconductor and hardware companies.