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Lauterbach presents leading debug solutions at the RISC-V Summit in Munich

By June 13, 2024June 17th, 2024No Comments

Hoehenkirchen, Germany – June 13, 2024 – Under the headline “RISC-V Debugging made Easy”, Lauterbach, the leading supplier of RISC-V debug and trace tools, will demonstrate at the RISC-V Summit in Munich how its TRACE32 debug and trace tools can support developers, even in complex scenarios.

Lauterbach, the world leader in debug and trace tools, has been a strategic member of the RISC-V Foundation since its inception and has made significant contributions to the RISC-V debug standard as well as to the future RISC-V trace standards for E-Trace and N-Trace.

Demo Theater Talk: “Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips

As part of the Demo Theater Talks, two of Lauterbach’s system engineers and RISC-V experts will present “Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips”. In this talk, they will show how developers can overcome any debug challenge in heterogeneous scenarios with the right tools and debug strategies. They will explain how cores from RISC-V and other architectures can be debugged simultaneously using a single debug interface and a single debug probe to gain insight into the entire embedded system. The presentation covers real-time on- and off-chip tracing for all major RISC-V trace systems as well as the use of standardized RISC-V debug and trace interfaces. All in all, the attendees will learn that multicore debugging with RISC-V cores is not rocket science and that there are efficient methods to master even complex chips with complex software configurations.

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