This panel will discuss the state of standardized cryptographic instruction set extensions for RISC-V processors. Lightweight instructions for scalar CPUs, high-performance instructions for vector CPUs, an entropy source interface, and “constant time” guarantees have been ratified. On-going work is in post-quantum cryptography and facilitating improved resistance to implementation attacks.
Moderator: Richard Newell, Microchip Technology Inc.
Panelists:
Nicolas Brunie, SiFive
Andrew Dellow, Consultant
Graeme Hickey, PQShield