With RISC-V processor architectures gaining traction across diverse computing systems, ensuring their reliability through rigorous verification becomes more crucial than ever. We have embraced a robust co-simulation strategy for verifying the NOEL-V RISC-V processor. This strategy integrates behavioural simulation with the SPIKE open-source RISC-V ISA simulator.
The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V is designed for space applications, targeting high-performance and fault-tolerance. The processor model offers many customization options and its advanced design required advanced verification strategies.