Last week’s RISC-V Summit in Santa Clara, Calif., had an air of confidence that we have not seen at previous summits. There was much for this tight-knit community to shout about. But overall, I heard words like “discipline” in the ecosystem quite often, meaning a collaborative effort to ensure baseline architectural foundations are maintained while adding customization and hardware-software co-design to ensure product development delivers on its expectations.
While the number of visitors might not have been huge, all the usual suspects on the RISC-V community gathered to highlight progress and market traction. The big news issued by RISC-V International was the ratification of the RVA23 Profile, for which key components are the vector extension for AI/ML and cryptography workloads, and the hypervisor extension to enable virtualization for enterprise workloads.
In her opening keynote, Calista Redmond, CEO of RISC-V International, said the number of SoC’s using RISC-V cores stood at two billion for 2024, and that would rise to 20 billion in 2031. As if to provide validation, Frans Sijstermans, VP for multimedia architecture at Nvidia, said in his talk that Nvidia was likely to ship over one billion devices using RISC-V cores in 2024.