Skip to main content

RISC-V Publications

This page has publications about RISC-V and ones that use or build on RISC-V. If you would like your publications added to this page, please feel free to contact


  • “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud,” Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018), Los Angeles, June 2018.





  • “The RISC-V Instruction Set,” Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David Patterson, Krste Asanovic, Poster at the Symposium on High Performance Chips (HotChips-25), Stanford, CA, August 2013.
  • “A Case for OS-Friendly Hardware Accelerators,” Huy Vo, Yunsup Lee, Andrew Waterman, Krste Asanovic, 7th Annual Workshop on the Interaction between Operating System and Computer Architecture (WIVOSCA-2013), at the 40th International Symposium on Computer Architecture (ISCA-2013), Tel Aviv, Israel, June 2013.



Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.