RISC-V Publications

This page has publications about RISC-V and ones that use or build on RISC-V. If you would like your publications added to this page, please feel free to contact community@riscv.org.

2018

• “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018), Los Angeles, June 2018.
• “OSEK-V: Application-Specific RTOS Instantiation In Hardware”, Christian Dietrich, Daniel Lohmann; Proceedings of the 2017 ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES ’17); ACM Press 2017.

2016

• “GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator”, Jan Gray 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016), May 2016.

• “RISC-V Offers Simple, Modular ISA”, D. Kanter, The Linley Group MICROPROCESSOR report, March 2016.

• “An Agile Approach to Building RISC-V Microprocessors”, Y. Lee, A. Waterman, H. Cook, B. Zimmer, B. Keller, A. Puggelli, J. Kwak, J. Bachrach, D. Patterson, E. Alon, B. Nikolic, K. Asanovic, IEEE Micro, March 2016.

• “A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI”, B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtić, B. Keller, S. Bailey, M. Blagojević, P. F. Chiu, H. P. Le, P. H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanović, B. Nikolić, IEEE Journal of Solid-State Circuits, March 2016.

• “SHAKTI Processors: An Open-Source Hardware Initiative”, N. Gala, A. Menon, R. Bodduna, G. S. Madhusudan, V. Kamakoti, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, India, January 2016.

• “Design of the RISC-V Instruction Set Architecture”, A. Waterman, Technical Report No. UCB/EECS-2016-1, EECS Department, University of California, Berkeley, January 2016.

2015

• “SHAKTI-F: A Fault Tolerant Microprocessor Architecture”, S. Gupta, N. Gala, G. S. Madhusudan, V. Kamakoti, 2015 IEEE 24th Asian Test Symposium (ATS), Mumbai, India, November 2015.

• “Towards General-Purpose Neural Network Computing – A Neural Network Accelerator for RISC-V Microprocessors”, S. Eldridge, A. Waterland, M. Seltzer, J. Appavoo, A. Joshi, 2015 International
  Conference on Parallel Architecture and Compilation (PACT), San Francisco, CA, October 2015.

• “The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor”, Celio, Christopher and Patterson, David A. and Asanović, Krste, Technical Report No. UCB/EECS-2015-167, EECS Department, University of California, Berkeley, June 2015.

• “A RISC-V Vector Processor with Tightly-Integrated Switched-Capacitor DC-DC Converters in 28nm FDSOI”, B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtic, B. Keller, S. Bailey, M. Blagojevic, P. F. Chiu, H. P. Le, P. H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanović, B. Nikolić, VLSI Circuits (VLSI Circuits), 2015 Symposium, Kyoto, Japan, June 2015.

• “RISC-V Out-of-Order Data Conversion Co-Processor”, A. Raveendran, V. Patil, V. Desalphine, P. M. Sobha, A. David Selvakumar, VLSI Design and Test (VDAT), 2015 19th International Symposium, Ahmedabad, India, June 2015.

• “Out-of-Order Floating Point Co-Processor for RISC-V ISA”, V. Patil, A. Raveendran, P. M. Sobha, A. David Selvakumar, D. Vivian, VLSI Design and Test (VDAT), 2015 19th International Symposium, Ahmedabad, India, June 2015.

• “GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation”, Chang Liu, Austin Harris, Martin Maas, Michael Hicks, Mohit Tiwari, Elaine Shi, 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2015), Istanbul, Turkey, March 2015.

2014

• “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators”, Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovc, Krste Asanovic, European Solid-State Circuits Conference (ESSCIRC-2014), Venice, Italy, September 2014.
• “The Case for Open Instruction Sets”, Krste Asanovic, David Patterson, MICROPROCESSOR report, August 2014.
  • ARM’s rebuttal to this article can be found at “The Case for Licensed Instruction Sets”, Ian Smythe, Ian Ferguson, MICROPROCESSOR report, August 2014.
• “Instruction Sets Should Be Free: The Case For RISC-V”, Krste Asanovic, David Patterson, Technical Report UCB/EECS-2014-146, EECS Department, University of California, Berkeley, August 2014.
• “A Case for MVPs: Mixed-Precision Vector Processors”, Albert Ou, Quan Nguyen, Yunsup Lee, Krste Asanovic, 2nd International Workshop on Parallelism in Mobile Platforms (PRISM-2), at the International Symposium on Computer Architecture (ISCA-2014), Minneapolis, MN, June 2014.
• “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0”, Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic, Technical Report UCB/EECS-2014-52, EECS Department, University of California, Berkeley, May 2014.
• “FlexPRET: A Processor Platform for Mixed-Criticality Systems”, Michael Zimmer, David Broman, Chris Shaver, Edward A. Lee, IEEE Real-Time and Embedded Technology and Application Symposium (2014), Berlin, Germany, April 2014.

2013

• “PHANTOM: Practical Oblivious Computation in a Secure Processor”, Martin Maas, Eric Love, Emil Stefanov, Mohit Tiwari, Elaine Shi, Krste Asanovic, John Kubiatowicz, Dawn Song, ACM Conference on Computer and Communications Security (CCS-2013), Berlin, Germany, November 2013
• “Hardware/Software Codesign for Mobile Speech Recognition”, David Sheffield, Michael Anderson, Yunsup Lee, Kurt Keutzer, 14th Annual Conference of the International Speech Communication Association (INTERSPEECH-2013), Lyon, France, August 2013.
• “The RISC-V Instruction Set”, Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David Patterson, Krste Asanovic, Poster at the Symposium on High Performance Chips (HotChips-25), Stanford, CA, August 2013.
• “Measuring the Gap between Programmable and Fixed-Function Accelerators: A Case Study on Speech Recognition”, Yunsup Lee, David Sheffield, Andrew Waterman, Michael Anderson, Kurt Keutzer, Krste Asanovic, Poster at the Symposium on High Performance Chips (HotChips-25), Stanford, CA, August 2013.
• “A Case for OS-Friendly Hardware Accelerators”, Huy Vo, Yunsup Lee, Andrew Waterman, Krste Asanovic, 7th Annual Workshop on the Interaction between Operating System and Computer Architecture (WIVOSCA-2013), at the 40th International Symposium on Computer Architecture (ISCA-2013), Tel Aviv, Israel, June 2013.

2012

• “Chisel: Constructing Hardware in a Scala Embedded Language”, Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic, Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.

2011

• “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA”, Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic, Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 2011. ]