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Advocates are RISC-V enthusiasts who work together with RISC-V International to ensure global momentum and adoption. Successful advocates include engineering students and early stage adopters who are passionate about sharing their knowledge and love of RISC-V with the community.
The program officially launched in March 2024 and will require an annual application, full details on how you qualify below.
RISC-V Advocates are individuals passionate about RISC-V and dedicated to growing and engaging the RISC-V community. The RISC-V Advocate Program empowers community members with tools and resources to:
Attributes of advocates: Passionate about sharing their knowledge and love of RISC-V. Ability to engage others in their local community and support the ecosystem through direct contributions.
Pre-Requirements to become a RISC-V Advocate:
Benefits of becoming a RISC-V Advocate:
RISC-V Advocates hold the title for 1 year and need to complete all requirements each year to continue in the program. Reassessment will happen in February and September of each year.
We are focused on creating a group of Advocates that meet all our requirements and represent our community and geographical diversity.
Questions? Reach out to local (at) riscv (dot) org
Expertise: RTL design, Functional Verification, FPGA, CPU core & memory subsystems, RISC-V privilege ISA, Energy Efficient NN Processor ISA, Neural Network Compiler/Kernel
Lahore, Pakistan
Abdul Wadood is a Hardware Engineer with expertise in Digital Systems and Computer Architecture. For over two years he has worked on the design and functional verification of RISC-V CPUs. He is experienced with Compiler and Kernel development for Energy Efficient Neural Network Processor Architecture. He has been an active member of the sig-arch-test group at RISC-V International and contributed to supporting the RISC-V privilege ISA testing in the standard Compatibility Test (ACT) framework. He is a former mentee at RISC-V International and Google Summer of Code and contributed to RTL design and verification efforts of notable open-source RISC-V cores (SERV, CVA6, and RocketChip). He holds a bachelor’s degree in Electrical Engineering with notable projects that include the ASIC implementation of an embedded RISC-V CPU and the RTL Design and Verification of a Linux-capable RISC-V CPU (UETRV_Pcore).
Expertise: General Linux Ecosystem, SBC Management, Software Enablement, Embedded Development
Located in Austin, Texas
Expertise: RISC-V | Design Verification | Computer Architecture
Lahore, Pakistan
Fatima Khurshid is currently working as a Senior Verification Engineer. Over the past four years, she has worked on the verification of RISC-V based processors. Fatima holds a degree in BSc. Electrical Engineering from the University of Engineering and Technology, Lahore. She has contributed in developing and reviewing the RISC-V Foundational Associate (RVFA) Certification.
Expertise: FPGA, SoC, VHDL, Computer Architecture, Embedded Systems
Ankara, Turkiye
Mehmet Burak Aykenar graduated from Electrical and Electronics Engineering of Middle East Technical University. He started research on digital design and computer architecture in his last year, then completed his masters degree from the Computer Engineering department of TOBB University of Economics and Technology. After some academic work he started working as a digital design engineer focused on FPGA based avionic systems. Currently he is working as a senior digital design engineer and his main work area is MCU/SoC IC design and FPGA based digital design. He gave lectures as a guest lecturer at various universities on digital design and computer architecture. He regularly publishes video lectures and blog writings about FPGA design, IC design and RISC-V through his YouTube channel and personal website.
Expertise: RISC-V, Formal Verification, Open-Source, CPU, GPU, RVFA
Toronto, Canada
Muhammad Bilal Sakhawat is a senior formal verification engineer. He has been verifying RISC-V based processors for more than 4 years. He holds a Bachelor of Science degree in Electrical Engineering from University of Engineering and Technology, Lahore. He has been an active member of the RISC-V Open-Source community since 2021. He made contributions to RISC-V Compliance Framework and RISC-V Sail (golden reference) Model. He also contributed to creating the RISC-V Foundational Associate (RVFA) exam.
Expertise: Computer Architecture, SoC Design, CHISEL HDL, Compilers, Embedded Software Engineering, EDA Tools Development
Karachi, Pakistan
Shahzaib Kashif is a Software Engineering Graduate from Karachi Pakistan. He is one of the pioneers who helped in establishing the Semiconductor Ecosystem in Pakistan with the introduction of RISC-V ISA in Undergraduate level via the Platform of Micro Electronics Research Lab (MERL). He is currently a Research Assistant at MERL, training juniors and leading teams of research interns towards a new era of computing and technology. He is part of the team that designed “SoC-Now”, which is a cloud-based System on Chip Generator, designed to help kickstart the chip design start-ups by providing them with a base level system just by a few clicks. He is also part of the team behind “ChipShop” which is a cloud-based GUI for accelerating SoC design, it uses Chipyard on its backend on the cloud. He has represented Pakistan internationally in RISC-V Summit of 2020, where he and his team presented a tutorial on “Reverse Engineering of Rocket-Chip”.
We send occasional news about RISC-V technical progress, news, and events.