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RISC-V in Verilog

By September 11, 2015No Comments

https://github.com/ucb-bar/vscale. This core implements a simple, Z-scale-class pipeline, and is designed for integration with either existing microcontroller-class bus interconnects or the Rocket chip generator. The build infrastructure for both flows will be publicly released with an upcoming update to the platform of small RISC-V systems compatible with Z-scale.]]>