Please note, RISC-V ISA and related specifications are developed, ratified and maintained by RISC-V International contributing members within the RISC-V International Technical Committee. Operating details of the Technical Committee can be found in the RISC-V International Tech Group. Work on the specification is performed on GitHub and the GitHub issue mechanism can be used to provide input into the specification.
The specifications shown below represent the current, ratified releases:
- Volume 1, Unprivileged Spec v. 20191213 [PDF] [GitHub (latest)]
- Volume 2, Privileged Spec v. 20190608 [PDF] [GitHub (latest)]
- External Debug Support v. 0.13.2 [PDF]
The processor trace specification was ratified in February, 2020.
The RISC-V Compliance Framework Version 0.1 is now available. This framework compares arbitrary models against a reference signature, and currently covers RV32IMC and RV64IMC unprivileged spec only. Work on Version 0.2 is underway.
The RISC-V spec allows many architectural implementation choices. A repository has been created to describe implementation configurations that the Framework will use to select & configure tests.