Please note, RISC-V ISA and related specifications are developed, ratified and maintained by RISC-V International contributing members within the RISC-V International Technical Committee. Operating details of the Technical Committee can be found in the RISC-V International Tech Group. Work on the specification is performed on GitHub and the GitHub issue mechanism can be used to provide input into the specification.

ISA Specification

The specifications shown below is the currentĀ ratified release. The most recent version of the draft specification, which is in development within the Technical Committee, can be found here on GitHub. You can also read it directly on this page.

Trace Specification

The processor trace specification was ratified in February, 2020. The latest draft can be found here on GitHub. A PDF is also available.

Compliance Framework

The RISC-V Compliance Framework Version 0.1 is now available

  • Compares arbitrary models against a reference signature
  • Currently covers RV32IMC and RV64IMC unprivileged spec only
  • Work on Version 0.2 is underway

The RISC-V spec allows many architectural implementation choices, a new repository created to describe implementation configurations that the Framework will use to select & configure tests.

Compliance GitHub repository: https://github.com/riscv/riscv-compliance/

Latest Compliance spec: https://riscv-config.readthedocs.io/en/latest/