In the world of processor development, flexibility is becoming a distinct advantage. As an open-standard instruction set architecture (ISA), the fifth iteration of reduced instruction set computing (RISC-V) embodies this…
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Munich, Germany — The European tech landscape is witnessing a notable evolution with the growing embrace of RISC-V, the open-source instruction set architecture. During the recent RISC-V Summit Europe, leading…
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As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I…
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The open-source RISC-V instruction set continues to make inroads across the electronics industry. Electronic Design’s and Microwaves & RF’s Bill Wong offer his take on the current status and future…
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With the ability to shift computing resources as needed, Microchip’s new 64-bit, RISC-V processors bring needed flexibility to embedded edge devices. Microchip has announced two new multi-core 64-bit MPUs operating…
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Microchip is qualifying an eight core fault tolerant RISC-V processor for AI in space applications. The radiation tolerant PIC64-HSPC octal core 1.2GHz switch provides 26K DMIPS and is built on…
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Microchip has launched its first 64bit microprocessor line, starting with a multicore RISC-V cluster for its PIC64GX family. The PIC64 GX1000 uses the existing RISC-V four core cluster with a…
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Munich, Germany — During the recent RISC-V Summit Europe, EE Times had the opportunity to talk to a leading RISC-V researcher Frank Kagan Gürkaynak, a senior scientist at ETH Zürich…
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European startup Vybium is developing am AI accelerator chip using the open RISC-V instruction set architecture to take on the Nvidia A100 GPU in the data centre. Vybium is a…
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In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we chip designers design various chips like simple embedded…
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