In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from Arm to RISC-V, new core customization features, and the latest advances in Capability Hardware Enhanced RISC Instructions (CHERI) memory protection.
Codasip focuses on three goals, Till-Vattier said: “One is making RISC-V cores easy to customize. Two is making them safe. And three is security.”
