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Own your silicon roadmap with RISC-V: The industry open standard for the software-defined vehicle.

The Software-Defined Vehicle Is Out of Beta.

For well over a decade, the software-defined vehicle (SDV) has represented a new model of mobility: one that transforms the car into a platform of over-the-air enhancements, on-demand personalization, and pervasive AI. In 2026, that vision has reached mass production. Cars are being bought and sold on the promise of a better experience in five years than on the day they leave the lot.

Automakers are decoupling software delivery from hardware production cycles, deploying and monetizing new features and services throughout a vehicle’s operational lifetime, analyzing performance, efficiency and maintenance requirements at a fleet-wide level, and designing vehicle ranges at a platform level, with each vehicle tuned to target a different market segment through software configuration alone.

How does RISC-V enable the software-defined vehicle (SDV)?

RISC-V’s modular, extensible ISA enables OEMs and Tier-1s to design AI-native, Workload-Specific Silicon that meets safety- and security-certification requirements. As an open standard, it eliminates restrictive licensing fees and reduces single-vendor lock-in, while fostering greater collaboration and Supply Chain Resilience. A multi-vendor ecosystem and OEM-governed roadmap give automakers long-term Economic Control across the entire software-defined vehicle (SDV).

Underpinning these outcomes is a consolidated E/E architecture that replaces proprietary, fixed-function electronic control units (ECUs) with a network of heterogeneous semiconductors, from highly deterministic microcontrollers (MCUs) at the edge, through high-performance, safety-critical processors that run advanced driver-assistance systems (ADAS) and autonomous driving workloads, to powerful infotainment SoCs in the digital cockpit.

Why RISC-V?

A Unified Hardware and Software Ecosystem Spanning the Entire Vehicle

The hardware underpinning the software-defined vehicle (SDV) must be capable of supporting an extraordinarily broad range of use cases, from the routine to the safety-critical. RISC-V goes further than any proprietary ISA in giving automotive OEMs and Tier-1s the freedom to design and deploy workload-specific silicon targeting every use case.

Whether deployed as a single-core microcontroller, a high-performance central compute platform, or a bespoke design that defies conventional categorisation, RISC-V supports any class of processor the SDV requires, handling every workload from deterministic control loops in braking systems to probabilistic AI in the digital cockpit.

What makes RISC-V so well-suited to software-defined vehicle design?

RISC-V’s modular, extensible ISA scales from a single core to thousands of Workload-Specific Silicon chips, spanning deterministic real-time safety loops through to complex probabilistic AI. Because every implementation is built on the same open standard, design teams can reuse software, tools, and engineering expertise across the vehicle instead of rebuilding between black-box ECUs or proprietary compute architectures.

One Instruction Set Architecture (ISA), Every Automotive Use Case

Guide Vehicle Back Into LaneStream Child's Audiobook to Rear OnlyStream Movie to Rear SeatsApply Brakes[IFMajor Impact DetectedDeploy AirbagsIsolate BatteryCall 911]Prompt Drive-Thru Order When Nearby[IFDriver Mood: TiredSuggest Nearby Coffee Stop]Reduce EV Charge Speed Above 85%Dip High BeamsLower Ride Height at SpeedInstall OTA Update OvernightReduce Front-Left Wheel TorqueConverse With Driver in Natural LanguageTighten Seatbelt on Hard CornerDim Interior LightingPre-Pay Toll on ApproachSync Ambient Light to Sunset[IFDriver Mood: SadSuggest 'Good Times' Playlist]Cool Driver SeatHeat Passenger Seat

Inherently scalable and extensible, RISC-V is also topology-agnostic: whether you’re targeting a domain or zonal architecture, or a measured transition between the two. The ISA champions consistency at every tier, giving automakers the capability to build on a standardized compute foundation to develop workload-specific silicon chips that meet the unique demands of their particular SDV vision, rather than mixing and matching closest-fit hardware from disparate vendor catalogs of proprietary IP. And as automakers begin to explore the merits of pervasive AI throughout the SDV – and the paradigm of the AI-defined vehicle (AIDV) – ratified RISC-V hardware profiles provide stable hardware targets upon which to design chips that meet every current and potential AI use case in the SDV.

Safety and security are fundamental pieces of the SDV puzzle, as the functions that steer, brake, and accelerate the vehicle move from fixed hardware into software. These workloads run on real-time, highly deterministic microcontrollers at the edge, governed by exacting standards such as ISO 26262 for functional safety and ISO/SAE 21434 for cybersecurity. RISC-V offers open, transparent foundations on which vendors can build their own implementations, certifiable for functional safety and cybersecurity.

Alongside these technical benefits, RISC-V provides tangible commercial benefits to automakers and Tier 1s. For example, the ability to source equivalent implementations from multiple suppliers without becoming dependent on any one vendor’s price list or roadmap.

At an ecosystem level, the result is a more resilient supply chain, in which RISC-V members align around a common architectural foundation while retaining the freedom to innovate, differentiate, and compete on price, performance, and value-add. This is the multi-sourcing and freedom from single-vendor lock-in that members consistently cite as central to the economic control RISC-V delivers.

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RISC-V for Automotive

Subscribe today for the latest industry insights on the Software-Defined VehicleEconomic ControlSupply Chain ResiliencePervasive AIWorkload-Specific SiliconSafety and Security


Economic Control

The Modular, Extensible RISC-V Architecture Puts Long-Term Cost Control in OEM Hands

  • Reduce development and operating costs by using one scalable RISC-V architecture, portable code, shared toolchains, and reusable engineering expertise across every class of automotive processor.
  • Protect vehicle differentiation and future revenue by co-designing hardware and software, adding custom instructions or workload-specific AI acceleration without adopting a generic, vendor-defined compute roadmap.
  • Preserve long-term commercial leverage through a royalty-free ISA* and competitive multi-vendor ecosystem, keeping sourcing options and pricing pressure in place throughout decade-plus vehicle programs.

How does RISC-V enable more precise economic control for automakers?

An open, modular ISA reshapes the financial math of automotive compute: no license fee or royalty on the ISA itself, the freedom to right-size each chip’s power, performance, and area to its exact workload, and shared toolchains across model tiers. That turns architecture-level choices into direct control over development cost, differentiation, and aftermarket revenue, rather than a single vendor’s roadmap.

RISC-V gives automakers greater control over automotive compute costs by providing one scalable architecture across the vehicle. Portable code, shared toolchains, reusable software, and common engineering expertise reduce development cost across processor classes and vehicle models, accelerating time to market while delivering a significant commercial advantage, protecting program economics and opening the door to aftermarket revenue over decade-plus program lifecycles.

The ISA’s extensible design enables OEMs to pay for the compute a workload actually needs, plus deliberately scoped headroom for foreseeable evolution. Each workload-specific silicon chip avoids paying for unused capability three times over: in die cost, energy consumption, and the cooling required to support it. OEMs can differentiate their designs rather than commoditize by adding standard and custom instructions, AI acceleration, or scalable cores and clusters without following one supplier’s roadmap. Meanwhile, IP ownership varies with how each processor is sourced, and licensing a commercial core, adopting an open-source design, or building bespoke silicon each set different terms for royalties, foundry choice, and end-of-life exposure.

Follow the link below to learn in detail how RISC-V gives OEMs and Tier 1s greater economic control.

Supply Chain Resilience

A Multi-Vendor Ecosystem Reduces Lock-In and Keeps Decade-Plus SDV Programs Resilient

  • Multi-source across vendors and geographies, reducing dependence on any one supplier, price list, roadmap, or region.
  • Protect decade-plus vehicle programs through a shared architecture, portable software, and comparable alternatives when supply is disrupted or components reach end of life.
  • Retain choice and differentiation by augmenting ratified RISC-V profiles with custom extensions, competitive sourcing across a multi-vendor ecosystem, and the option to pursue greater vertical integration.

How does RISC-V strengthen automotive supply chain resilience?

An open standard ISA enables silicon and IP vendors of every scale, across every region, to build automotive processor solutions on the same architecture. That widens customer choice, drives a more competitive marketplace, reduces the supply risk of single-vendor exposure, and helps maintain lifecycle continuity across 10–15 year vehicle programs.

Automotive OEMs have long managed extensive multi-vendor supply chains, and their commercial success has often depended on managing those chains for stability, choice, and resilience. Semiconductors have become the hardest link to manage on those terms: in the traditional model, the processor architecture inside a vehicle’s electronics is the commercial property of a single licensor, and every sourcing decision downstream inherits that dependency.

RISC-V removes that inherited dependency at the root. Because extensions and ratified profiles are modular features of an open standard rather than one vendor’s product, many silicon and IP vendors can each design their own workload-specific silicon to the same architecture, and OEMs can mitigate shortages by sourcing from more than one of them. The result is a fully owned automotive roadmap.

Those options matter most over time. Today’s vehicle platforms are designed to last ten years but may stay on the road for fifteen to twenty more. The vibrant RISC-V ecosystem turns a re-platforming exercise into a sourcing decision.

We’ve built a page on Supply Chain Resilience, exploring component availability, vehicle lifecycles, the global vendor market, roadmap control, and the thriving ecosystem that maintains the RISC-V open standard itself.

Pervasive AI

Decentralized AI Compute Processes Data Locally for Lightning-Fast Reaction Times

  • Deploy AI across every compute tier, from physical AI in safety microcontrollers, sensors and zonal controllers to agentic AI in central compute and the digital cockpit.
  • Combine types and functions of AI using RISC-V’s extensible scalar, vector, and matrix capabilities, with hardware virtualization isolating workloads carrying mixed-criticality safety obligations across shared silicon.
  • Build the AI-defined vehicle (AIDV) on one open foundation, using RISC-V profiles and combining standard and custom architectural extensions to match each workload-specific chip to the intelligence, power, and safety requirements of its role.

How does RISC-V enable the compute architecture for the AI-defined vehicle (AIDV)?

Pervasive AI works because one open, AI-native ISA runs across every processor in the vehicle: automakers match Workload-Specific Silicon to each job on a single shared architecture rather than fitting software to a patchwork of proprietary designs. That same ISA is what enables intelligence to reach from the digital cockpit to the safety-critical edge, evolving the SDV into the AI-defined vehicle (AIDV).

Pervasive AI is intelligence that spans interconnected workloads throughout the SDV. Physical AI perceives the world and acts in real time, from sensor fusion and perception in central compute to deterministic control loops in safety microcontrollers at the edge, where latency is measured in milliseconds and failure has safety consequences. Agentic AI personalizes the digital cockpit through conversational voice, navigation, and orchestration. The two increasingly contribute to the same use cases and coexist on mixed-criticality silicon. Each workload runs on workload-specific silicon, right-sized to its needs rather than one proprietary accelerator.

For functional safety workloads, AI remains bounded: RISC-V privilege levels, memory protection, and deterministic execution support anomaly detection and predictive maintenance within a safety island, while certified control retains final authority over braking, steering, and power delivery. RISC-V provides certifiable mechanisms, while member implementations earn certification. Adding AI through an industry open standard also enables multi-supplier sourcing, strengthening supply chain resilience and giving OEMs greater economic control of their SDV programs as AI takes a growing share of overall vehicle cost.

Our page on Pervasive AI covers RISC-V in physical AI at the edge, agentic AI in the digital cockpit, the new paradigm of the AI-defined vehicle, and where bounded inference belongs in safety-critical systems.

Workload-Specific Silicon

Purpose-Built Chips for Every Vehicle Workload, Unified by One Open ISA

“We knew RISC-V’s long-term success would stem from uniting disparate use cases and diverse industries around a common, open architecture. We designed the ISA to be inherently extensible, enabling chipmakers to create their own workload-specific silicon. That unique combination of a shared foundation and the freedom to optimize for specific workloads is proving vital for automotive, where one size rarely fits all.”

Krste Asanović
Krste Asanović, Chief Architect, RISC-V
From “RISC-V and the Road to Workload-Specific Silicon” — RISC-V Blog
  • Shape each processor to its workload by starting with RISC-V’s minimal base ISA and adding only the ratified or custom extensions its capability envelope requires.
  • Create diverse automotive processors on one shared architecture using RISC-V profiles that bundle extensions such as Vector for AI, Hypervisor for mixed-criticality consolidation, and Scalar Cryptography for secure boot.
  • Balance PPA efficiency with long-term headroom using modular RISC-V capabilities that meet today’s requirements while preserving a stable software target across future silicon implementations.

How does the RISC-V ISA enable vendors to design workload-specific silicon?

RISC-V provides one extensible instruction set architecture to standardize on: a minimal core instruction set augmented by ratified profiles, which bundle standard hardware extensions, or vendor-specific custom extensions. Designers can therefore tailor each chip to its workload, from a deterministic microcontroller to an AI-capable application processor, while reusing software, tools, and engineering expertise across purpose-built silicon throughout the vehicle.

RISC-V enables hardware designers to shape each processor to specific workloads to meet SDV use cases by combining capabilities traditionally associated with microcontrollers, application processors, and neural processors. Each chip can devote its power, performance, and area (PPA) budget only to the tasks its target workload requires, improving performance per watt, reducing die size and cost, and delivering more predictable latency. Across an SDV’s many compute nodes, these efficiencies compound within tight thermal and power limits and across the millions of units shipped over a vehicle platform’s lifetime.

Notably, ‘workload-specific’ does not mean designing only for day-one requirements. Vendors must build-in sufficient compute headroom, memory bandwidth, and hardware capability to support foreseeable functions throughout the vehicle’s lifecycle. RISC-V profiles provide common, versioned baselines for software portability, while standard and custom extensions let designers add the capabilities each workload and its anticipated evolution require. This balances efficiency today with flexibility for tomorrow, without defaulting every compute node to an oversized general-purpose processor.

Our Workload-Specific Silicon page covering heterogeneous compute, RISC-V profiles, and the standard and custom extensions that shape each chip to its workload.

Safety and Security

Architectural Transparency Provides Certifiable Foundations for Functional Safety and Cybersecurity

  • Build certifiable automotive silicon on an industry open standard, with standardized privilege levels, memory protection, and precisely defined exception behavior providing the architectural foundation.
  • Isolate mixed-criticality workloads and protect vehicle software using ratified Hypervisor and Scalar Cryptography extensions for domain separation, secure boot, and authenticated updates.
  • Keep AI advisory at the safety-critical edge using RISC-V privilege levels and memory protection to isolate inference within a safety island while a deterministic, certified control loop keeps final authority over braking and steering, not the AI.

How can automakers ensure that the chips in a software-defined vehicle operate safely and securely?

As steering, braking, and acceleration become increasingly software-defined, a silicon fault or cyberattack can become a safety hazard. RISC-V provides an open, fully documented ISA with standardized privilege levels, memory protection, cryptography, and virtualization. Chip vendors and system integrators can implement these mechanisms in certifiable processors that isolate mixed-criticality workloads, protect software and data, and support secure boot and authenticated updates.

Physical electronic systems with the SDV depend on the correct operation of the silicon and software beneath them, making functional safety fundamental. The same logic extends to cybersecurity: a connected, updatable vehicle is exposed to malicious actors, and a security weakness can become a safety hazard. Both disciplines are heavily regulated and non-negotiable for any component that performs, or connects to one that performs, mission-critical workloads.

RISC-V’s open, fully documented ISA gives silicon vendors, toolchain providers, and system integrators a transparent architectural foundation for implementations targeting ISO 26262 ASIL requirements and vehicles subject to UN R155 and R156. The architecture underlying a safety or security case is published and freely available rather than hidden behind a vendor NDA. This transparency also supports a resilient supply chain: an OEM or Tier 1 evaluating a second source can assess it against familiar architectural terms. Reusing a shared ISA, software ecosystem, tools, and engineering expertise may also reduce duplicated re-engineering or re-certification work across chip families, helping OEMs maintain greater economic control over compliance processes that can otherwise run to tens of millions of dollars per platform.

Throughout the RISC-V Automotive Hub, you’ll find guidance on building automotive silicon to meet these stringent certification requirements.

Frequently Asked Questions

The Questions We’re Often Asked about RISC-V in Automotive

The term software-defined vehicle (SDV) entered industry lexicon in the mid-2010s, as OEMs began to recognize that the benefits to both vendor and end user of software-defined devices like smartphones could apply to cars, too. In an SDV, functionality is abstracted from the underlying silicon. The hardware becomes a general-purpose compute substrate; the intelligence lives in software, and can be changed and updated wirelessly ‘over the air’ (OTA), just as your phone informs you “update installed.”

RISC-V is an open standard ISA that scales from ultra-low-power embedded processors to high-performance central compute using a single architecture across all vehicle domains. It is not controlled by any single company, enabling multi-sourcing and long-term platform independence – both important properties for programs spanning ten or more years.

No. RISC-V International standardizes the instruction set architecture; it does not productize the ISA or design and license processor cores. That role belongs to IP vendors and chip designers, who build their own roadmaps on the standard. Anyone is free to design a conformant RISC-V chip, and software written for one conformant processor should run cleanly on another.

RISC-V is openly licensed and not controlled by any single silicon company. OEMs and Tier 1s can source equivalent RISC-V implementations from multiple vendors across different geographies, preserving procurement flexibility and negotiating leverage. Switching silicon suppliers does not require rebuilding the software stack – the ISA remains constant across all compliant implementations.

Yes. RISC-V scales from ultra-low-power embedded processors in body control and sensor applications, through domain and zonal controllers, to high-performance centralized compute running AI inference workloads. A single open architecture spans this entire range, enabling consistent toolchains, shared debug environments, and software portability across the full vehicle.

The RISC-V Automotive Special Interest Group brings together OEMs, Tier 1 suppliers, silicon vendors, and software partners to define requirements, share best practices, and coordinate automotive-specific RISC-V profiles and extensions. Membership is open to all RISC-V International members. The Functional Safety SIG addresses architecture requirements relevant to safety-focused implementation teams in parallel.

RISC-V International is the non-profit standards body that stewards the open standard RISC-V ISA, maintaining the specification and ratifying its extensions and profiles. It does not design, license, or sell processor cores; that role belongs to the IP vendors and chip designers who build conformant silicon on the standard.

RISC-V Automotive Hub

The open standard architecture for smarter and more scalable automotive compute.

Economic Control

Preserve cost competitiveness and roadmap ownership throughout decade-plus vehicle platform programs.

Supply Chain Resilience

Source equivalent implementations from multiple vendors across geographies, without depending on any one price list or roadmap.

Pervasive AI

Deploy intelligence throughout the vehicle, spanning voice assistants in the digital cockpit, ADAS and automated driving, and physical AI in microcontrollers.

Workload-Specific Silicon

Standardize on a single architecture for every workload, with a software stack spanning every purpose-built chip in the vehicle.

Safety and Security

Design certifiable silicon on open, transparent foundations to meet exacting functional safety and cybersecurity standards.