Skip to main content

RISC-V Summit North America 2025 · Santa Clara, California - Oct 22-23 · Register Now

search
Ecosystem News

Smart public transportation system using VEGA Processor [ RISC-V ISA] | VEGA Processors

By February 21, 2021No Comments

Demonstrating Smart public transportation system using VEGA Microprocessor based on RISC-V ISA

Subscribe for updates, event info, webinars, and the latest community news

By submitting this form you are consenting to receive marketing emails about news, events, and training from RISC-V. You can unsubscribe at any time by following the “Subscription Center” link included within such communications. For information on our privacy practices and commitment to protecting your privacy, please review our Privacy Policy. We do not sell your contact information to third parties.

About
Technical Steering Committee
Board of Directors
FAQ
Contact Us
About RISC-V
History of RISC-V
Blog
News
Announcements
Genealogy
Policies
Privacy Policy
Code of Conduct
Antitrust Policy
Brand Guidelines
Specification
Ratified
Under Development
Contribute
Developers
Get Started
Training
Development Partners
Developer Boards
Labs
Mentorship
Technical Wiki
Industries
Automotive
Artificial Intelligence
Case Studies
Exchange
Landscape
Software Ecosystem Dashboard
Events
RISC-V Summit
Calendar
Videos
Community Meetings
Members
Current Members
Resources
Recognition
Resources
Get RISC-V Gear
Join RISC-V International
Becoming a member of RISC-V International allows companies and individuals to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs.
JOIN NOW