RISC-V at ESSCIRC-2014

We have presented our paper “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators” at the 40th European Solid-State Circuits Conference, which was held at Venice, Italy. This paper details our 45nm test chip, which has two 64-bit RISC-V Rocket scalar cores, each with a Hwacha vector accelerator attached to it. The paper and the talk will be available online shortly.