Imperas Software Ltd., the leader in verification solutions for RISC-V, and Codasip, the leader in customizable RISC-V processor IP, today announced that Codasip has adopted Imperas reference designs and the Imperas DV solution for Codasip IP. Codasip has invested heavily into processor verification to deliver the industry’s highest quality RISC-V processors.
Codasip has included Imperas golden reference models in its DV testbenches to ensure an efficient verification flow that accommodates a wide range of flexible features and options while scaling across the entire roadmap of future cores to enable rigorous confirmation of functional quality.
RISC-V is a modular architecture that offers many different permutations of base instructions, standard optional extensions and custom instructions – that raises concerns about implementations and the risk of fragmentation. Codasip’s internal testing already uses an internal instruction-accurate model, several sources of direct and random testing (internal and externally provided), and several different technologies to check and ensure processor compliance. Imperas configurable reference models are already fully tested and enable all the configuration options needed to support this comprehensive view.