Technical Steering Committee

Greg is Co-Founder and CTO of Ventana Micro Systems.

Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL, a company providing outsourced R&D for semiconductor companies: services range from tools for pre-silicon architectural exploration to the building of software ecosystems .

Avi works in CPU Architecture and Design at Google.

Bing Yu has been an active contributor to the RISC-V ecosystem since 2022 and currently participates in more than 10 RISC-V International (RVI) Special Interest Groups (SIGs) and Task Groups (TGs). He serves as Co-Chair of the IME Task Group.Bing is Senior Technical Director at Andes Technology, where he leads processor roadmap strategy, architecture development, and product design. He brings more than 30 years of experience in technical leadership, processor architecture, and system design, with deep expertise in machine learning hardware, high-performance CPU design, and scalable system architectures.

Bing earned a Bachelor of Science in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Prior to joining Andes Technology, Bing served as SoC Architect for the camera subsystem at Meta. Before that, he was a Mobile Architect at MediaTek and led the development of high-performance coherent processor systems at Nvidia. Earlier in his career, he held processor engineering roles at Intel and Motorola, where he established a strong foundation in advanced processor design and computer architecture.

Derek Zhang is the Director of RISC-V Standardization & Industry Dept in Huawei. He is specializing in leading RISC-V resources across both hardware design and software solutions and responsible for driving strategic initiatives aimed at expanding in various verticals, including Consumer Electronics, Smart Home, and Automotive, through innovative solutions.

Dr. Fujie Fan currently serves as Senior R&D Director at Stream Computing, Inc., where he is leading the design of high-performance AI training and inference chips based on RISC-V architecture and the development of its open-source ecosystem. As an active contributor to the RISC-V community, he led the design of the first RISC-V Matrix instruction set, and realized a superscalar RISC-V CPU core integrating both Matrix and Vector extensions, along with the development of supporting toolchains such as compilers and simulators. The related technical documentation and software/hardware codes have been open-sourced on GitHub and released to the RISC-V community. Prior to joining Stream Computing, Dr. Fujie Fan worked as a Senior Researcher at Huawei Technologies, where he conducted pioneering research on computing-in-memory architectures and AI processor design. He has led the design and tape-out of multiple high-performance computing acceleration chips, possessing extensive experience in chip design and computer architecture

Earl is CTO of Aril Inc. In his career he has worked as a software engineer (operating systems, compilers, and networking) and microprocessor architect. He graduated from MIT in 1978 (B.S. Electrical Engineering and Computer Science), first working on software at BBN and LLNL, and subsequently in software and microprocessor design at MIPS, QED, SGI, and Tensilica, all silicon valley companies engaged in creating microprocessor products for both general-purpose and embedded computing as well as some experience in HPC. Earl was a co-founder and CTO of QED, and held the title Director of Architecture at each of the other companies. His microprocessor work has resulted in 34 patents issued so far. He has been involved in the specification of several Instruction Set Architectures.

Erich is working as Fellow at OpenChip, doing hardware, system and software architecture. He has a PhD in theoretical physics from RWTH Aachen and has worked in computational physics, numeric algorithms research, distributed systems, Linux kernel development, system, software and hardware architecture R&D at NEC HPC Europe. He is a long time vector computing advocate and excited about the democratization of computer hardware through RISC-V.

Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.

Full Professor of Computer Science and Engineering at the University of Campinas (UNICAMP). Member of the technical advisory board of Eldorado and SIDI R&D Institutes and the CI-Brasil Council at the Brazilian Ministry of Science and Technology. Co-founded companies Kryptus and Idea! and is a member of the Editorial Board of IEEE MICRO. His current interests include code optimization, parallelizing compilers, and compiling for accelerators targeting RISC-V, which are explored in close cooperation with industrial partners.

As head of RISC-V core development at ESWIN Computing, I drive the design and implementation of cutting-edge RISC-V processors architectures and lead cross-fuction teams to deliver scalable, customizeable RISC-V IP cores for diverse applications, including AIoT, automotive, and edge computing.

Guy has been a Professor in Computer Engineering at the University of British Columbia for over 20 years where I teach advanced digital design and computer systems/architecture related courses. My undergrad and graduate degrees are all from the University of Toronto. I’ve built processors from scratch (RISC-V and others), co-founded VectorBlox Computing where we developed the MXP (Matrix Processor) as a vector accelerator for RISC-V and other ISAs. In grad school, I co-designed custom designed cache-coherent multiprocessors that were built from MIPS R4400 CPUs and custom PCBs and FPGA circuitry. My research focuses on improving FPGA devices and CAD tools, in particular making them easier to use for computing tasks. I was a member of the RISC-V Vector Committee and the early Cache Management Operations committee, and I chair the RISC-V SoftCPU SIG. I’ve also given several talks at RISC-V meetings.

Hongbin Zhang is a postdoctoral researcher at the Institute of Software, Chinese Academy of Sciences. He received his Ph.D. degree from the University of Chinese Academy of Sciences. His research focuses on compiler technology and software-hardware co-design techniques. As an MLIR contributor, he is actively exploring the integration between the MLIR framework and the RISC-V ecosystem.

Jian Zhang is a Product Manager at BOSC, specializing in high-performance computing IP, including CPU, NoC and others. Prior to joining BOSC, Jian accumulated over 15 years of experience as a software engineer, working extensively in operating systems for both server and embedded systems. His deep expertise in software and hardware integration.

Jianlin Gao is the Director of panglai laboratory in Tencent . He is a expert in IC and OS software, developed the edge AI chip“penglai” and cloud side AI chip “zixiao” as main architect , also designed the codec chip “canghai”, support H265 and H266 encode.

Dr. Kan Shi is currently an Associate Professor at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include agile chip design, reconfigurable computing, and cloud data center architecture.

Dr. Shi earned his PhD from Imperial College London, and then worked at Intel UK R&D center as an SoC Design Engineer, with focus on developing FPGA-based SmartNIC/DPU/IPU and their applications in cloud data centers.

Ken continues to be passionate about RISC-V and all of its potential!

Since 2018 he has actively contributed to the RISC-V community through serving on the Board of Directors and the Technical Steering Committee, heading several Task Groups, authoring several ISA extensions, contributing to many TGs & SIGs, and making multiple presentations at RISC-V Summits and Workshops. In his day job, he has played a key role in the development and optimization of several RISC-V implementations.

Ken is a Senior Principal Architect at Tenstorrent where he defines high-end RISC-V processors and systems.

Ken has over 37 years of experience in computer architecture and development, and has over three dozen patents.

When not helping develop the RISC-V architecture, implementing RISC-V designs, helping develop new floating point standards (IEEE P3109 and IEEE-754), or developing processor benchmarks (SPEC OSG), Ken can be found spending time with family, fiddling with antique phonographs, and playing classical guitar.

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Marcel Tromp is a Fellow at Infineon Technologies where he drives platform architectures and methodologies as well as processor strategy, including RISC-V adoption.

Marcel started his career at Philips Research as a VLIW CPU architect and later served as chief architect at TriMedia and Equator Technologies. He has held both senior technical and managerial roles defining and delivering complex SoC’s at LSI Logic, Magnum Semiconductor and Cypress Semiconductor.

Marcel holds a MSc. in Electrical Engineering from the University of Twente in the Netherlands.

Shi is at Sanechips/ZTE.

Tom is a Technical Expert at Phytium.

Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.

Zhong Su, Ph.D. AI Scientist, Alibaba DAMO Academy
With over two decades of pioneering research in artificial intelligence, Dr. Zhong Su has built a distinguished career spanning industry leadership and academic excellence. He currently serves as an AI Scientist at Alibaba DAMO Academy, following his tenure as Head of the Future Technology Center at Alibaba Research, where he steered the group’s technical strategic research. Previously, Dr. Su was the Head of AI at IBM Research – China, leading breakthroughs in natural language processing, speech technologies, and machine learning. In 2018, he was elected a Member of the IBM Academy of Technology.

Complementing his industry impact, Dr. Su is a Guest Professor at Nankai University and Shanghai Jiao Tong University. He has authored over 100 papers in premier international venues with 10,000+ citations and holds over 100 patents. His accolades include the 2020 ACM SIGKDD Test of Time Award and multiple IBM Outstanding Technical Achievement Awards. He currently serves as an Executive Committee Member of the China Computer Federation Technical Committee on Artificial Intelligence. Dr. Su holds a Ph.D. in Computer Science from Tsinghua University.