First, some background. RISC V is an open-source instruction set architecture (ISA), a “free” alternative to Arm. ISAs provide a set of common, important but unglamorous “blueprints” for processors. Every processor needs what an ISA provides to do some basic math. They take a lot of work to design and maintain but do not provide much end-product differentiation, which means that the chip companies who use them see great advantage in outsourcing this work to a third party like Arm.
