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SiFive Adds RISC-V Micro-Instruction Cache For Slow Memories | Steve Bush, Electronics Weekly

SiFive has added a ‘micro instruction cache’ option to its Risc-V e2 core – the smallest of its Risc-V intellectual property offerings.
article: https://www.electronicsweekly.com/news/design/eda-and-ip/sifive-adds-risc-v-micro-instruction-cache-slow-memories-2019-10/
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