Join us at the RISC-V Workshop Taiwan from Tuesday, March 12 to Wednesday, March 13, 2019 at the Ambassador Hotel in Hsinchu City, Taiwan. The RISC-V Workshop Taiwan will showcase the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA), with a focus on the momentum and growth of the RISC-V ecosystem across China and Asia. There will be sessions, demonstrations and poster presentations from member companies Andes Technology, Codasip, Cryptape, Hex-Five Security, MediaTek, Microsemi, a wholly owned subsidiary of Microchip Technology Inc., Nuclei System Technology, SiFive, Software Hardware Consulting (SH Consulting), Syntacore and Western Digital.
Tuesday, March 12, 2019 RISC-V Workshop Taiwan
| Time | Event | Speaker, Affiliation |
| 8:00 | Registration is open from 8:00 – 17:00 | |
| 8:30 | Welcome & Foundation Overview | Rick O’Connor, RISC-V Foundation |
| 8:45 | Keynote: Andes Technology | Andes Technology |
| 9:15 | Panel: Opportunities & Challenges in AIoT | Frankwell Lin, Andes Technology; Steve Lo, Egis Technology Corp; Ted Speers, Microchip Technology; Chen-Yi Lee, National Chiao-Tung University; Zvonimir Bandic, Western Digital |
| 10:00 | Networking Break | |
| 10:30 | RISC-V Technical Committee Update | RISC-V Foundation |
| 10:45 | RISC-V Marketing Committee Update | Ted Marena, RISC-V Foundation Marketing Committee and Western Digital |
| 11:00 | Status update of RISC-V P extension task group | Chuan-Hua Chang, Andes Technology |
| 11:15 | Simulation Evaluation of Chaining Implementation for the RISC-V Vector Extension | Zhen Wei and Wei-Chung Hsu, National Taiwan University |
| 11:40 | Lunch & Networking Break | |
| 13:00 | RISC-V Segmentation Extension Proposal | Wuyang Chung, Freelancer |
| 13:15 | MediaTek RISC-V Processor on Sensorhub Application | Jeremy Liu, MediaTek |
| 13:45 | New Members of AndeStar V5 Processor IPs | Charlie Su, Andes Technology |
| 14:15 | Our Passion on the Popularization of RISC-V | Tony Xu, Nuclei System Technology |
| 14:40 | Networking Break | |
| 15:10 | Platform Security–A Detailed Comparison of RISC-V to ARM’s TrustZone | Don Barnetson, Hex Five Security |
| 15:40 | Cryptospec: a Trust Module System for 64-bit RISC-V Core Complex | Shumpei Kawasaki, SH Consulting; Cong-Kha Pham, University of Ellectro-Communication |
| 16:10 | Energy-Efficient Face Detection Using Andes RISC-V Processor | Chien-Hao Chen and Po Yu Huang, National Chiao Tung University (NCTU) |
| 16:25 | A Different World: a Blockchain-Focused, General-Purpose Applicable Software Sandbox System Based on RISC-V | Xuejie Xiao, Cryptape Technology |
| 16:55 | Enabling TVM on RISC-V Architectures with SIMD Instructions | Allen Lu, Peakhills Group Corporation; Jenq-Kuen Lee, National Tsing-Hua University |
| 17:25 | Poster Preview Sessions | |
| 17:40 | Networking Reception |
Wednesday, March 13, 2019 RISC-V Workshop Taiwan
| Time | Event | Speaker, Affiliation |
| 8:00 | Registration is open from 8:00 – 9:00 | |
| 9:00 | Diamond Sponsor Keynote | |
| 9:30 | The Updated Status of RISC-V SW | Kito Cheng and Greentime Hu, Andes Technology |
| 10:00 | RISC-V Perf Tool Status | Alan Kao, Andes Technology |
| 10:15 | Linux on RISC-V — Fedora and Firmware Status Update | Wei Fu, Red Hat |
| 10:40 | Networking Break | |
| 11:10 | Toolchain: Compiler Support for Linker Relaxation in RISC-V | Shiva Chen and Hsiangkai Wang, Andes Technology |
| 11:40 | Toolchain: Enhanced LLVM Support For RISC-V | Zdenek Prikryl, Codasip |
| 12:10 | Toolchain: RISC-V Configurability in Compliance Test Framework | Radek Hajek and Milan Skala, Codasip |
| 12:35 | Networking Lunch | |
| 14:05 | Datacenter Processors with OmniXtend Interfaces for Shared Memory and AI Workload Acceleration | Zvonimir Bandic, Western Digital |
| 14:50 | PolarFire SoC FPGA — AMP Capable Solution for Both Deterministic Real-Time and Rich OS Support | Vishakh Rayapeta, Microsemi |
| 15:05 | Enabling Embedded Intelligence | Jack Kang, SiFive |
| 15:35 | SCRx Family of the RISC-V Compatible Core IP by Syntacore | Alexander Redkin and Pavel Khabarov, Syntacore |
| 16:05 | Closing Session |