RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

Fast Track significantly accelerates the ratification of small architecture extensions

Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions. ZiHintPause is the first extension to be ratified under this new process.

Fast Track defines the process for developing and standardizing architecture extensions that meet specific criteria, while providing reasonable quality control under the oversight and approval of the relevant RISC-V standing committee. Fast Track is designed for extensions that are simple, uncontentious, offer value to a large portion of the RISC-V community, and cleanly fit into existing RISC-V architecture. Once an extension has been submitted for consideration it will undergo an internal review before entering a 45-day public review process.

“The Fast Track system enables us to more quickly address the needs of the RISC-V community as the diversity of RISC-V solutions and applications continues to grow exponentially,” said Mark Himelstein, CTO, RISC-V International. “The ratification of ZiHintPause demonstrates how this simplified process significantly accelerates the review of important extensions, while still maintaining RISC-V’s core tenant of openness with a public review period.”

The ZiHintPause extension enables engineers to reduce the energy consumption of their designs. The extension also helps improve the performance of spin-wait loops and enable multithreaded cores to temporarily relinquish extension resources. The ZiHintPause extension adds a single PAUSE instruction (encoded as a HINT instruction) to the ISA.

“We architected the ZiHintPause extension to improve the energy efficiency of synchronization code in system software,” said Andrew Waterman, Privileged Architecture Task Group Chair at RISC-V International and Chief Engineer at SiFive. “It’s a cost-effective and versatile extension that’s also well suited to a variety of other use cases where low-power operation is important.”

“This is an important extension for the RISC-V ISA, so we are happy to see that ZiHintPause was able to be ratified quickly and is now available for the whole RISC-V community to use,” said Greg Favor, Co-Founder and CTO, Ventana Micro Systems. “Fast Track maintains the necessary checks and balances to ensure extensions are properly designed and adhere to RISC-V’s architectural approach, while paving the way for RISC-V International to rapidly expand its set of standardized extensions.”

To learn more about the Fast Track Architecture Extension Process, please visit: https://docs.google.com/document/d/1UD8p_I9KcqhAGPhrfnUpx1onw3D3Ou_–HxduhC7TXo/edit

To view the ratified ZiHintPause extension, please visit the Unprivileged ISA spec: https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20210212-c879d5a

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About RISC-V International

RISC-V is a free and open ISA enabling a new era of processor innovation through open collaboration. Founded in 2015, RISC-V International is composed of more than 1,200 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

RISC-V International, a non-profit organization controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of RISC-V International have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.