anisha

As a participant at the recent RISC-V Summit in Shanghai, I witnessed firsthand the sheer scale and unwavering resolve with which China is strategically investing in and developing its domestic…

Silicon Valley, CA – August 6th, 2025 – Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. RiscFree provides comprehensive visibility and…

Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting…

Raja Koduri, a legendary GPU architect from ATI Technologies, AMD, Apple, and Intel, on Tuesday said he had founded a new GPU startup that emerged from stealth mode today. Oxmiq Labs is…

For decades, chip architectures have been dominated by a pair of towering incumbents—x86 and Arm—defining and powering everything from laptops to hyperscale data centers. But in recent years, the open-standard…

As semiconductor applications continue to diversify, the traditional one-size-fits-all processor model is becoming increasingly outdated. Today’s designs demand greater specialization to meet the unique performance, power, and cost requirements of…

Nvidia announced it is working to bring CUDA platform support to the RISC-V instruction set architecture (ISA) at the 2025 RISC-V Summit in China, with the goal of enabling RISC-V…

Some high-performance RISC-V processors are in the pipeline for the rest of the year 2025, namely UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3. We currently have limited information about each…