Register for the Upcoming RISC-V Workshop in Barcelona: May 7-10, 2018

About the WorkshopRegistration is now open for the RISC-V Workshop in Barcelona, co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) May 7-10, 2018. The event will be sponsored by NXP and Western Digital.As with past workshops, this event will bring together the RISC-V community to share RISC-V activities underway around the globe, and build consensus on the future evolution of the instruction set. Co-Hosted By …

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A Look Back at the Evolution of RISC-V and a Peek at What’s Next from Krste Asanović

This post was written by Krste Asanović, Chairman of the Board of the RISC-V FoundationI still remember the first public RISC-V rollout at Hot Chips in August 2014, where our gaggle of Berkeley students and faculty wore bright blue RISC-V t-shirts and asked passerby to come see our demo silicon and grab a RISC-V button. The t-shirts are a little worse for wear, but the free and open RISC-V ISA…

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Charting a New Course for Semiconductors

The Global Semiconductor Alliance has released a new report “Charting a New Course for Semiconductors” which explores the future of the semiconductor industry and asks “Is RISC-V the new Linux?”.                               Global Semiconductor Alliance Releases New ReportThe report includes 4 Chapters covering key areas including: Chapter 1 – An Industry in Transition – Rising development costs, decreasing margins and…

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RISC-V in Verilog

V-scale, an implementation of an RV32IM core in Verilog has been released and is available at: https://github.com/ucb-bar/vscale.This core implements a simple, Z-scale-class pipeline, and is designed for integration with either existing microcontroller-class bus interconnects or the Rocket chip generator. The build infrastructure for both flows will be publicly released with an upcoming update to the platform of small RISC-V systems compatible with Z-scale.

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RISC-V Foundation Incorporated!

The RISC-V Foundation has been officially incorporated! For more information about joining the RISC-V Foundation, please contact Rick O’Connor, Executive Director via email at rickoco@riscv.org.

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RISC-V Draft Compressed ISA Version 1.7 Released

The RISC-V Compressed Instruction Set Manual Version 1.7 Draft proposal has been released and is available at this link. You can also download a PDF version at this link.We welcome community feedback and comments on this draft. In particular, we offer two options of what RVC should be. Thus, we need your feedback in order to decide which path to take. (The report lists the pros and cons of each…

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