RISC-V: An Open Approach to System Security

By Helena Handschuh, Security Technologies Fellow at Rambus Inc. and Chair of the RISC-V Foundation Security Standing CommitteeLeveraging open source technology delivers great benefits for software and hardware development, but also for security.In one of this year’s RSA Conference keynotes, it was described how managing open source software is getting more and more complicated because of the difficulty of backtracking to origins when a software bug or a security bug…

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RISC-V is not an “open-source processor” | Krste Asanovic, Chairman of the Board, RISC-V

Free and open standards are common in the computing industry, with instruction sets being an odd exception where the industry has tolerated proprietary interfaces, until now.  With the excitement around the arrival of the free and open RISC-V instruction set architecture (ISA), many are a little confused about the difference between a specification and an implementation.  There is no such thing as “the RISC-V core” — there are dozens of…

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RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020 

The RISC-V Foundation booth will include live demonstrations and talks of RISC-V implementations from fourteen membersWHERE: Hall 3A, Booth No. 3A-536, NürnbergMesse, Messezentrum 1, 90471 Nürnberg, GermanyWHEN: Tuesday, Feb. 25 – Thursday, Feb. 27, 2020WHAT: At Embedded World 2020, the RISC-V Foundation will be exhibiting at Hall 3A, Booth No. 3A-536, and will feature live demonstrations from co-exhibiting RISC-V Foundation members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, Embecosm, GreenWaves Technologies, Imperas Software, Intrinsic…

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RISC-V Foundation & Members At Embedded World 2020

Join us at the Embedded World 2020 Exhibition & Conference from Tuesday, Feb. 25 to Thursday, Feb. 27, 2020 at the NürnbergMesse in Nuremberg, Germany. Visit Our Booth Featuring Fourteen RISC-V MembersThe RISC-V Foundation booth will feature fourteen pods from RISC-V members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, Embecosm, GreenWaves Technologies, Imperas Software, Intrinsic ID, OneSpin Solutions, OpenHWGroup, SiFive, Syntacore and UltraSoC. Visit us in Hall 3A, Booth No. 3A-536….

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RISC-V Summit Videos Posted

The videos from the RISC-V Summit are now posted on the Summit Proceedings page, with a few exceptions we will fix as soon as possible. Enjoy! 

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Curated List of RISC-V Education Materials Now Available

The RISC-V Foundation is committed to helping developers and members grow and expand their use of the RISC-V ISA, and access to training materials and educational materials is a fundamental part of empowering the ecosystem and driving innovation.That is why today the RISC-V Foundation is pleased to announce the first iteration of the RISC-V Educational Materials section on the Foundation’s website. Created thanks to the collaborative work of the University…

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RISC-V Foundation Seeks Technology Leader

The RISC-V Foundation is looking for a technology leader who can foster a successful technical ecosystem with deep member and community engagement and meaningful progress across technical imperatives in growing adoption of the RISC-V architecture. The technology leader will facilitate the technical vision, cultivate stakeholder engagement, and drive the strategy in collaboration with RISC-V members. This person will be the Foundation’s technical leader in facilitating progress across our workgroups and…

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Final Countdown to RISC-V Summit in San Jose

The RISC-V Summit in San Jose starts on Monday, December 9. There is still time to register for both the Summit itself and the all-members working day on December 9, but the window is closing soon. This Summit will bring together the principal movers and shakers in the hardware industry. This is not an event to miss.For more information and details on the event, please see the agenda page. If…

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Announcing the Winners of the RISC-V Soft CPU Contest

As the number of connected devices skyrockets, the attack surface also increases. To solve the growing challenge of mitigating cybersecurity threats, every component in a system must be evaluated for its vulnerabilities. Processors today are able to run billions of instructions per second – this means you can access a world of content at your fingertips, but there’s also a risk of exploitation. Every processor requires built-in security features to…

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RISC-V EMEA Roadshow Spotlight: Imperas

The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting free, half-day “Getting Started with RISC-V” events in Tel Aviv, Munich, Berlin, Tallinn, Paris and London from Sept. 16-26. RISC-V Foundation members will give presentations and live demonstrations showcasing innovation RISC-V solutions and implementations. Register today to save your spot!Imperas is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verification and Customization of RISC-V Cores and SoCs.”…

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