SEGGER has expanded the capabilities of its debugger and performance analyzer, Ozone by adding semihosting support for debugging RISC-V applications. This feature now enables RISC-V developers to use I/O to perform debugging…
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Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise hardware, operating systems and software workloads Santa Clara, Calif.…
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The RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing together innovators, developers, and thought leaders who are driving advancements in open computing. Taking place…
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Hello everyone! A month and a half ago, we wrote about the latest status of the RISC-V DynaRec (Dynamic Recompiler, which is the JIT backend of Box64) and shared the gratifying progress…
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The open-source revolution is expanding beyond software into hardware design. New microcontrollers from Microchip Technology and Espressif incorporate processors based on RISC-V—an open-source instruction set architecture challenging Arm’s dominance in connected devices. RISC-V,…
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It’s an exciting time to be involved in open source. Linux powers the world’s most critical devices, a story to which Red Hat has always been a champion. Today we…
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The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for those interested in shaping the future RISC-V and open standards. From groundbreaking innovations to in-depth…
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LDRA has extended support for the RISC-V instruction set architecture (ISA) in its high assurance quality analysis and verification tool suite. The LDRA static analysis tools support emerging RISC-V implementations such as…
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Nick Flaherty talks to Calista Redmond, CEO of RISC-V International, on how the European Chips Act is driving the open instruction set architecture forward. “The recent European summit showed the…
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Lauterbach has extended their industry leading TRACE32® debug and trace tools to include support for Synopsys’ RISC-V instruction set based ARC-V™ processor IP, which includes full debug and trace, including…
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