Soooo… you’ve decided you’re going to create a system-on-chip (SoC) device of such awesomeness that it will leave your competitors gnashing their teeth and rending their garb. You’ve also decided…
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Semidynamics in Spain has developed a customisable 4-way RISC-V 64bit core for data centre chips. The Atrevido 423 RISC-V core has a wide 4-way pipeline for decoding and retiring twice…
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RISC-V was one of the key themes at DAC 2023. We had a RISC-V Zone where six members discussed their latest RISC-V activities, and there were a ton of RISC-V…
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Andes’ new deep-learning accelerator addresses convolutional neural networks in edge applications. Accompanied by vector CPUs, it forms an AI subsystem that can be scaled up for higher vision- and audio-workload…
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By: Kezia Leung The RISC-V Summit Europe brought together members of the RISC-V community from industry, government, research, and academia to explore how RISC-V is shaping the future of innovation.…
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Author: Meng Chang This topic presents an example about how to deploy a YOLOX model on a RISC-V development board for object detection. The content of this topic is derived…
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Data and codes are only as powerful as the security platform that protects them. Without a robust security model for isolated code execution and data protection, developers and their platforms…
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At this year’s Design Automation Conference (DAC), there was a panel discussion entitled, “Delivering on RISC V’s Promise to Give Designers Freedom to Innovate – What’s Needed?”. A key message…
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Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic…
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Limerick, Ireland – July 14, 2023 – Ashling today announced its RiscFree SDK has been added to the Lattice Semiconductor RISC-V ® MC CPU soft IP support ecosystem. RiscFree is…
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