As announced at the first annual RISC-V Summit, the RISC-V Foundation honored the winners of the RISC-V SoftCPU Contest for creating innovative FPGA based CPU implementations targeting the RISC-V ISA. Thanks to everyone who participated in the RISC-V SoftCPU Contest! We were excited to see the innovative entries and appreciate your feedback on how we can continue to improve contests in the future.
 
Congratulations to the winners:

• 1st Place: Charles Papon with VexRiscv was awarded $6,000 USD
• 2nd Place: Antti Lukats with Engine-V was awarded $3,000 USD, a Splash Kit and an iCE40 UltraPlus MDP
• 3rd Place: Changyi Gu with PulseRain Reindeer was awarded $1,000 USD, a PolarFire Evaluation Kit and an iCE40 UltraPlus Breakout Board.
• Creativity Prize: Olof Kindgren with SERV was awarded $3,000 USD

 
And a special thanks to the contest sponsors Google, Antmicro, Lattice Semiconductor and Microchip.
 
A Closer Look at the Winning Entries
The first place entry, VexRiscv, was the highest-performance Microsemi implementation and Lattice implementation. Charles’ VexRiscv impressively scaled down, ranking as the third smallest Lattice implementation, while also scaling up to be a Linux capable core. Additionally, the core was selected to be used in Western Digital’s RISC-V Linux Hackathon at the RISC-V Summit!
Antti’s Engine-V design was the smallest Microsemi implementation and Lattice implementation, and earned second place in the contest overall. The Engine-V entry used miniscule 306 x 4 input LUTs on the iCE40 UltraPlus MDP, an impressively small number to implement a fully RV32I-compliant implementation. Antii also gets a special shout-out for his excellent support of other participants.
PulseRain Reindeer took third place overall. Changyi’s PulseRain Reindeer design ranked second for the highest-performance Microsemi implementation, and third for the smallest Microsemi implementation and highest-performance Lattice implementation.
Olof took home the Creativity prize with his bit serial implementation of a RISC-V core. This open source demonstration of doing bit serial with a fully open ISA is a great addition to the ecosystem. Check out his post about the project here.
 
Honorable Mentions
We would also like to recognize the following projects for their innovations: Jörg Mische with Danzig, Matthew Ballance with Featherweight and Frederic Requin with JiVe. Check out Matthew’s write-up about his Featherweight core here. 
About the Contest
The aim of the contest was to promote innovative vendor-independent, modular and reusable FPGA applications. The participants were challenged to build extremely small, extremely powerful, softcore RISC-V implementations, with additional points awarded for novel approaches to the implementation itself.
Designs needed to be a complete FPGA implementation targeting at least one of the two platforms from Microsemi or Lattice, and run the provided Linux Foundation Zephyr RTOS application. The Linux Foundation and RISC-V Foundation recently announced a joint collaboration to accelerate open source development and adoption of the RISC-V ISA. This partnership with the Linux Foundation will enable the RISC-V Foundation to grow the RISC-V ecosystem with improved support for the development of new applications and architectures across all computing platforms.
The contest was judged by representatives from Antmicro, Google, Lattice, Microsemi and the RISC-V Foundation.
 
The Winners’ Scores
 

Scoring Breakdown